JFE2325 Dual Low-Power N-Channel JFET

Introduction

Texas Instruments’ JFE2325 is a dual low-power N-channel JFET designed as a monolithic matched pair for very high-impedance sensor interfaces. Integrating two matched devices on one die helps support circuits where channel-to-channel consistency matters, while its self-biased gate arrangement is intended to simplify direct coupling to suitable signal sources.

The device is notable for combining greater than 400GΩ input impedance with just 0.85pF input capacitance per JFET. These characteristics make it suited to interfaces involving low-capacitance transducers and other high-impedance sensors, where the input stage should place minimal loading on the source.

What it does

The JFE2325 contains two N-channel JFETs, with integrated diodes that bias their gates. This self-biased approach enables direct signal-source coupling without requiring a gate bias resistor.

Each JFET has an input capacitance of 0.85pF and the pair is specified for input impedance above 400GΩ. The device provides a transconductance of 0.7mS at a 385µA full-drain current. For noise-sensitive front ends, the specified noise figure is -110dBV A-weighted with 5pF input capacitance.

Matching is an important characteristic of the dual device: maximum VGS mismatch is specified as 30mV, while maximum IDSS mismatch is 5%. The JFE2325 also specifies a 30V gate-to-drain breakdown voltage and an operating temperature range of –40°C to +125°C.

Applications

Potential uses that follow from the device’s high-impedance, low-capacitance input characteristics include:

• Input stages for high-impedance sensor interfaces
• Interfaces for low-capacitance transducers
• Microphone interface circuits
• Matched dual-JFET analog front ends
• Differential or paired sensor-input circuits where JFET matching is relevant

Design considerations

The JFE2325 is supplied in a compact 0.8mm × 1mm X2SON package, which can support very space-constrained sensor-interface designs but requires consideration of fine-pitch PCB layout and assembly capability.

Its integrated gate-bias diodes eliminate the need for a gate bias resistor in the intended direct-coupled configuration. Designers should nevertheless account for the specified 30V gate-to-drain breakdown limit, the 385µA condition associated with the stated transconductance, and the input capacitance of each JFET when evaluating source loading and front-end bandwidth. For paired circuits, the specified VGS and IDSS mismatch limits provide relevant matching boundaries.

Availability and further information

The source and distributor links on this page provide further information on the JFE2325. The linked Texas Instruments datasheet should be consulted for complete electrical characteristics, test conditions, pin information, and circuit implementation guidance.