RZ/G3L Quad Core MPUs

Introduction

Renesas RZ/G3L is a family of entry-class human-machine interface (HMI) microprocessors built around up to four Arm Cortex-A55 application cores and an Arm Cortex-M33 sub-CPU. The combination is notable for bringing Linux-capable processing, real-time operation, graphics, video handling, camera input, and industrial networking into a compact MPU family.

With Cortex-A55 cores operating at up to 1.2GHz and a 200MHz Cortex-M33, the RZ/G3L devices are positioned for systems that need a rich graphical interface while also accommodating lower-level control tasks. Integrated H.264 encode/decode, a Mali-G31 GPU, and support for Full HD displays provide a foundation for display-centric embedded designs.

What it does

The RZ/G3L family supports Linux-based HMI platforms and RTOS operation. Its main processing complex comprises four Arm Cortex-A55 cores, while the Arm Cortex-M33 sub-CPU can be used alongside the main application processors.

For graphics and multimedia workloads, the MPU integrates an Arm Mali-G31 3D GPU rated at 7.2 GFLOPS and H.264 hardware encoding and decoding. A single display channel supports MIPI-DSI, single-channel LVDS, or parallel display interfaces, with display support up to 1920 × 1080 at 60 frames per second. A MIPI CSI-2 interface is available for camera connectivity.

The connectivity set includes one-lane PCIe Gen2 at 5.0GT/s, two USB 2.0 host/function OTG interfaces, and two Gigabit Ethernet interfaces with IEEE 802.1 TSN support. An external bus interface supports 8-bit and 16-bit random access, with stated bandwidth of approximately 133MB/s at 133MHz CKIO under normal access without wait states.

Security and reliability features described for the family include ECC, Renesas Secure IP, secure boot, Arm TrustZone, secure debug, and tamper detection. The devices also support DDR self-refresh for 1mW-class standby power consumption.

Applications

• Linux-based industrial HMI panels with Full HD display output
• Operator interfaces that combine touchscreen/display functionality with camera input
• Networked embedded systems requiring dual Gigabit Ethernet and IEEE 802.1 TSN support
• Edge-interface equipment using PCIe, USB 2.0, or an external parallel bus
• Embedded designs that separate application processing on Cortex-A55 cores from control-oriented tasks on the Cortex-M33 sub-CPU

Design considerations

RZ/G3L devices are supplied in LFBGA package options: a 17mm × 17mm, 0.65mm-pitch, 368-pin package and a 14mm × 14mm, 0.5mm-pitch, 400-pin package. Board layout and assembly processes therefore need to accommodate fine-pitch BGA routing and the selected package footprint.

System architects can select among MIPI-DSI, LVDS, and parallel display connections, but the family provides one display support channel. Camera designs need a compatible MIPI CSI-2 interface. The available I/O also enables designs to plan for PCIe, dual Ethernet, USB OTG, and external memory or peripheral access through the 8-bit or 16-bit external bus.

The specified operating junction-temperature range is -40°C to +125°C. For software planning, the supplied information identifies support for the CIP Linux SLTS kernel v6.12 with long-term maintenance support, alongside RTOS-capable operation through the Cortex-M33 sub-CPU.

Availability and further information

The source/distributor link on this page provides further information on the Renesas RZ/G3L Quad Core MPUs. Consult the linked datasheet for detailed electrical characteristics, interface implementation requirements, package drawings, and device-specific information.