Diodes Incorporated has released the PI6CG33A06, a six-output PCIe clock generator built for PCIe 7.0 systems running at 128GT/s. The device is aimed at servers, networking hardware, HPC systems, and AI platforms where distributing clean reference clocks across large PCIe fabrics is becoming harder with every new interface generation.
The PI6CG33A06 is a low-jitter clock generator that produces 25MHz and 100MHz reference clocks for PCIe devices. It supports PCIe 5.0, PCIe 6.0, and PCIe 7.0 clock requirements, with RMS jitter specified below 30fs for PCIe 7.0 common-clock operation. PCIe timing budgets get uncomfortable once link speeds start climbing this high. A little extra noise from routing, connectors, switches, retimers, or the clock source itself can start eating into margin surprisingly quickly, especially once several devices are sharing the same clock structure across a dense server board.
Sub-30fs Jitter Leaves More Timing Margin
Diodes specifies less than 30fs RMS jitter for PCIe 7.0 operation. The PCIe 7.0 specification allows up to 67fs, so the PI6CG33A06 sits well below the limit. That extra margin matters because the clock source is only one part of the timing chain. The signal still has to move through PCB traces, vias, connectors, switches, retimers, and endpoint devices before the link finally closes properly at the receiver side. At 128GT/s, engineers are not just routing clocks anymore. They are managing accumulated timing error across the whole path. The device supports either a 25MHz crystal or an external XO, TCXO, or OCXO input, depending on how the timing architecture is being built and what frequency stability requirements the system needs to meet.
Six Differential Outputs For PCIe Clock Distribution
The PI6CG33A06 provides six differential output pairs using 85Ω differential drivers. Three outputs are fixed at 100MHz, one is fixed at 25MHz, and two outputs can be configured for either frequency. That layout makes practical sense for modern server boards where different sections of the platform may need different reference clocks. Storage, networking, switches, accelerators, and host processors do not always end up sharing the exact same timing requirements. Each output also includes individual enable control.
In larger PCIe systems, that gives designers a cleaner way to shut down unused sections of the clock tree instead of leaving every output active permanently. The device also supports Intel CK440Q specifications and provides SMBus programmability with multiple SMBus addresses and tri-level address selection.
Integrated Termination Removes External Resistors
Diodes uses its LP-HCSL output structure with integrated termination inside the PI6CG33A06. According to the company, this cuts clock-related power consumption by at least 50% compared with traditional HCSL implementations. It also removes the need for up to 24 external resistors. That may not sound dramatic, but clock routing around modern PCIe layouts is already crowded enough. Pulling a couple dozen resistors out of the routing area can make placement easier around switches, retimers, connectors, and accelerator packages where board space disappears quickly. Less surrounding circuitry also means fewer opportunities to introduce routing compromises around sensitive clock paths.
The PI6CG33A06 runs from a 3.3V supply across a -40°C to +85°C operating range and is supplied in a 40-pin, 5mm × 5mm VQFN package. Diodes lists pricing from $2.80 in 3,000-piece quantities.
Learn more and read the original announcement at www.diodes.com
Technology Overview
The Diodes Incorporated PI6CG33A06 is a six-output PCIe clock generator for PCIe 5.0, PCIe 6.0, and PCIe 7.0 systems. The device generates 25MHz and 100MHz reference clocks with PCIe 7.0 RMS jitter below 30fs. It uses LP-HCSL outputs with integrated termination, supports SMBus programmability, and operates from a 3.3V supply in a 40-pin VQFN package.
Frequently Asked Questions
What is the PI6CG33A06 used for?
The PI6CG33A06 is used to generate low-jitter PCIe reference clocks for servers, AI accelerators, networking hardware, HPC systems, and data center platforms.
What PCIe standards does the PI6CG33A06 support?
The device supports PCIe 5.0, PCIe 6.0, and PCIe 7.0 clock requirements.
Why does PCIe 7.0 need lower clock jitter?
As PCIe link speeds increase to 128GT/s, the available timing margin becomes smaller, so clock jitter contributes more directly to overall link stability and signal integrity.
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