As chips continue to get smaller, many are left wondering when exactly this shrinkage will stop. Recently, TSMC announced it will be rolling out A14 devices by 2028, meaning that we still have a long way to go.
TSMC to Manufacture A14 Devices by 2028
Recently, TSMC announced that it will be moving forward with its next generation of semiconductor process technology, called A14, with mass production expected in the second half of 2028. This process will allow for the creation of advanced AI accelerators, smartphones, laptops, and high-performance computing devices, while continuing TSMC’s dominance in the semiconductor industry.
The new process, called A14, will follow TSMC’s upcoming N2 process, which is expected to introduce next-generation transistor technology. While there are currently limited details surrounding the A14 process, TSMC has stated that it will provide up to 15% better performance than N2 at the same power consumption, or alternatively, up to 30% lower power usage while maintaining similar performance.
Additionally, A14 will also allow more transistors to be packed into the same physical area, increasing overall computing capabilities without requiring larger chips. This is especially important as AI workloads continue to grow and require processors capable of handling increasingly complex models.
According to TSMC, the new process has already received strong interest from customers, with demand being driven largely by the rapid expansion of AI applications. Modern AI systems require massive amounts of computing power, and this has created significant demand for more efficient and powerful semiconductor technologies.
TSMC has also stated that A14 development is progressing ahead of schedule, with improvements in both device performance and manufacturing yields. The process will build upon advancements in Gate-All-Around (GAA) transistor technology, which provides improved control over current flow compared with traditional transistor designs.
How Much Further Can We Go?
At the A14 process node individual chips can contain hundreds of billions of transistors. However, even with such a tiny manufacturing process, we are still not yet at the absolute limits of semiconductor technology.
But exactly how far can we continue shrinking transistors? When will reducing transistor size stop providing meaningful improvements? These are questions that many scientists and engineers continue to investigate, and while there are no definitive answers yet, there are several limitations that provide some clues.
To start, there will eventually be a point where making transistors smaller no longer provides a worthwhile benefit. Modern semiconductor manufacturing relies on incredibly precise imaging systems, and as transistor dimensions approach atomic scales, producing reliable structures becomes increasingly difficult.
Furthermore, smaller transistors are also more vulnerable to manufacturing defects and quantum effects. When features become only a handful of atoms wide, even minor variations can significantly impact performance and reliability, making the technology harder and more expensive to manufacture.
However, one of the biggest challenges comes from the imaging systems themselves. As semiconductor features become smaller, manufacturers require increasingly advanced lithography equipment, such as extreme ultraviolet (EUV) systems. These machines are already some of the most complex and expensive devices ever created, and future generations may become economically impractical.
Because of this, it is likely that the industry will eventually move away from simply shrinking transistors and instead focus on technologies such as 3D stacking. Rather than making individual transistors smaller, engineers can stack multiple layers of processors, memory, and other components together, dramatically increasing computing density.
In fact, 3D stacking could introduce an entirely new wave of technological advancement, allowing devices to become more powerful without requiring smaller transistor dimensions.
So, how much further can we go? It is difficult to say, but personally, I believe that practical limits could be reached around 2030, when further reductions in transistor size become too expensive and difficult to justify. At that point, 3D stacking will likely become the dominant approach, giving engineers an entirely new direction for the future of computing.
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