Nvidia's next AI bottleneck might not be the chip itself

Image credit: Nvidia

Nvidia has announced a major expansion of its semiconductor supply chain, with plans to increase package substrate capacity by 2.5 times over the next three years. The company is also supporting a substantial increase in advanced packaging and testing capacity, with six manufacturing partners involved in the agreements.

The announcement, made at GTC Berlin on October 21, includes Samsung Electro-Mechanics, Ibiden, Unimicron, Amkor, King Yuan Electronics and Siliconware Precision Industries. Amkor alone is preparing to increase interposer wafer capacity by more than 300% by the end of 2028, while Nvidia expects its total semiconductor testing capacity to double between 2026 and 2027.

What's interesting about these agreements is that they don't involve manufacturing the processor dies themselves. Instead, Nvidia is investing in the facilities needed to package, connect and test those processors before they can be delivered to customers.

With modern AI accelerators combining enormous processors, multiple HBM stacks and increasingly complicated power delivery systems, it appears that making the silicon is no longer the only major manufacturing concern.

Nvidia moves to expand advanced packaging capacity

The largest part of Nvidia's announcement concerns package substrates, with Ibiden, Samsung Electro-Mechanics and Unimicron all involved in expanding production.

Ibiden is developing additional capacity at its Ono facility in Japan, with production expected to begin increasing during the first quarter of 2028. Unimicron is expanding its manufacturing operations in Taiwan, while Samsung Electro-Mechanics will supply substrates from South Korea under a new multi-year agreement.

Samsung's involvement is particularly interesting because the company has also provided some details about the technologies needed for Nvidia's next-generation processors.

The substrates use Ajinomoto Build-up Film, or ABF, an insulating material that allows manufacturers to produce extremely fine copper connections across multiple layers. These connections are used to route signals and power between the semiconductor package and the circuit board on which it is mounted.

Interestingly, ABF was originally developed by the Ajinomoto Group, the Japanese company better known for its food products and seasonings. Its work with amino acid chemistry eventually led to the development of specialised insulating films for semiconductor manufacturing, with the material first entering commercial use in 1999.

Today, ABF is widely used in high-performance processor substrates, including those found in servers and AI hardware. It allows manufacturers to create very fine circuit patterns using processes such as laser drilling and copper plating, providing the connections needed between the densely packed semiconductor dies and the larger external connections.

For Nvidia, the manufacturing challenge is becoming more difficult as its processors grow larger and incorporate more components. A modern AI accelerator can contain a large logic processor alongside several HBM stacks, often connected using a silicon interposer. The complete assembly then needs a package substrate capable of carrying the electrical connections, distributing power and supporting the structure.

One problem identified by Samsung Electro-Mechanics is substrate warpage.

Silicon, copper and the organic materials used in a package all respond differently to temperature changes. As the assembly is heated during manufacturing, these differences in thermal expansion can cause the substrate to bend or distort.

This becomes troublesome when dealing with large packages containing thousands of closely spaced electrical connections. A substrate that isn't sufficiently flat can create alignment problems during assembly, while mechanical stress can affect the reliability of solder joints and other connections.

Samsung is developing techniques to improve substrate flatness and reduce warpage, alongside finer circuit patterning for increasingly complicated semiconductor packages.

Another development mentioned in Samsung's announcement is the integration of passive components directly into the substrate. These include multilayer ceramic capacitors and silicon capacitors, which can be used to improve power integrity by reducing electrical noise and unwanted voltage fluctuations.

Instead of relying entirely on capacitors mounted elsewhere in the system, manufacturers can position some of the required capacitance much closer to the processor. Shortening the electrical path reduces parasitic inductance, which becomes increasingly important when supplying processors with large and rapidly changing current demands.

Samsung hasn't said that every one of these technologies will appear in Nvidia's forthcoming products, but it shows how much functionality is being incorporated into what was once regarded primarily as a means of connecting the silicon to a circuit board.

Beyond substrates, Nvidia has also reached an agreement with Amkor to expand advanced packaging in South Korea. This includes additional interposer processing capacity, with new manufacturing facilities planned to support future AI platforms.

Semiconductor testing is another area receiving investment. Nvidia is providing a $1.1 billion capacity reservation advance to King Yuan Electronics, or KYEC, to support new testing facilities in the United States, with high-volume production targeted for April 2027.

The company is also working with Siliconware Precision Industries to expand production of optical engines used in co-packaged optics. Nvidia is targeting a 15-fold increase in that capacity by mid-2027, helping support the growing communication requirements of large AI computing clusters.

Why packaging could become a problem for AI manufacturers

There is an interesting manufacturing problem behind Nvidia's decision to secure so much additional capacity.

Producing a working semiconductor die doesn't automatically mean that it can be turned into a working processor package. This is especially true for devices using multiple pieces of silicon, where each component must be correctly positioned, connected and tested.

Consider an AI accelerator containing a large GPU and eight HBM stacks. The logic die and memory may have been tested individually before assembly, but there are still numerous opportunities for something to go wrong when the components are brought together.

A connection defect, damaged interposer or assembly fault could leave the complete package unusable, even though the individual semiconductor dies were manufactured correctly.

The cost of such a failure can be substantial. Modern AI processors are expensive to manufacture, while HBM stacks involve multiple memory dies and their own complicated assembly processes. Losing a finished package containing all those components is very different from discovering a defective die before packaging begins.

This also makes manufacturing yield particularly important. If a manufacturer wants to double its output, it needs more than twice the available equipment if a significant proportion of the additional assemblies fail testing. Improving capacity without maintaining acceptable yields could become an expensive exercise.

Large package substrates make the problem harder. More surface area is needed for each device, reducing the number that can be manufactured from a given panel. The greater size also makes it more difficult to maintain accurate alignment and control mechanical distortion during assembly.

Then there are the electrical requirements. A package containing powerful processors and HBM needs to distribute large amounts of current while maintaining clean power and high-speed signal integrity. The position of a capacitor, the length of a connection or the properties of the substrate material can influence whether the completed system operates reliably.

This is why Samsung's work on embedded capacitors is particularly interesting. Engineers designing ordinary PCBs already know the importance of keeping decoupling capacitors close to their devices. At the power levels and switching speeds involved in advanced AI hardware, manufacturers are taking that principle further by moving some of the capacitance into the package itself.

Of course, there is still the question of whether Nvidia will need all the capacity its partners are planning.

Much of the expansion won't be fully available until 2027 or 2028, and semiconductor manufacturing facilities represent enormous investments. If demand for AI processors grows more slowly than expected, suppliers could find themselves with expensive equipment that isn't operating at full capacity.

On the other hand, Nvidia faces a different problem if demand continues to grow and packaging capacity cannot keep up. Having additional GPU dies available is of little help if there aren't enough substrates, interposers or testing facilities to turn them into products.

I think this is what makes the announcement particularly significant. Nvidia is already working with some of the world's most advanced semiconductor manufacturers, yet it is now making substantial financial commitments to secure the components and manufacturing processes surrounding those chips.

It also shows how advanced packaging has developed into an engineering discipline of its own. A package containing multiple silicon dies, HBM stacks, fine-pitch connections and embedded passive components is a considerable achievement, even before considering the processor architecture inside it.

For engineers, the interesting part is that some of the biggest challenges are now appearing in places that rarely receive much attention during a product launch. The next generation of AI processors might offer enormous improvements in computing performance, but delivering them in sufficient quantities could depend just as heavily on the quality of the substrate beneath them.