Achronix Semiconductor Corporation has released a new JESD204C IP core for its Speedster7t FPGA family, providing an interface between high-speed analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and programmable logic. Each core supports data rates up to 32 Gbps per lane and an aggregate serial line rate up to 256 Gbps.
For designs requiring more bandwidth, up to four cores can be combined to reach 1 Tbps. The IP works with high-speed JESD204B and JESD204C converters from suppliers including Analog Devices and Texas Instruments, with JESD204B compatibility retained for existing converter designs.
High-Speed JESD204C Connectivity
Developed for high-bandwidth, multi-channel converter systems, the JESD204C IP supports 64b/66b and 8b/10b encoding, along with forward error correction (FEC), CRC-12 and CRC-3 modes.
Subclass 1 with deterministic latency supports phase-coherent synchronization in single and multi-channel systems. Flexible framing, integrated alignment and recovery features are also included, along with an AXI-Lite interface for control.
The IP uses the Speedster7t FPGA family's 112 Gbps SerDes to support 32 Gbps JESD204C links. Speedster7t devices also feature a two-dimensional network-on-chip (NoC) for moving data across the FPGA and embedded GDDR6 memory controllers offering up to 4 Tbps of aggregate memory bandwidth.
JESD204C for 5G, Radar and Test Systems
Achronix is targeting the JESD204C IP at wireless infrastructure, aerospace and defense, test and measurement, and high-speed data acquisition.
Applications include direct-RF transceivers and massive-MIMO systems for 5G and 6G, radar and electronic warfare, high-bandwidth oscilloscopes, digitizers and automated test equipment.
Medical imaging and scientific instrumentation are also among the target applications, where high-rate sampling is combined with real-time signal processing.
Development and Availability
The IP package includes synthesizable VHDL and Verilog design files, templates and example designs. A graphical interface is provided through the Achronix ACE design environment, while simulation tools and testbenches are also included. Hardware-tested demonstrations provide configuration scripts for Achronix VectorPath accelerator cards.
The Achronix JESD204C IP core is available now for Speedster7t FPGAs. Achronix also offers a free, time-limited evaluation version of the IP core.
Learn more and read the original announcement at achronix.com.
Technology Overview
The Achronix JESD204C IP core connects high-speed ADCs and DACs to Speedster7t FPGAs. It supports up to 32 Gbps per lane, deterministic latency, JESD204B backward compatibility and encoding and error correction options for high-bandwidth converter systems.
FAQs
What is the Achronix JESD204C IP core?
It is an IP core for connecting high-speed JESD204B and JESD204C ADCs and DACs to Achronix Speedster7t FPGAs.
What data rates does the JESD204C IP support?
The IP supports data rates up to 32 Gbps per lane and aggregate serial line rates up to 256 Gbps per core. Up to four cores can be combined for aggregate performance up to 1 Tbps.
Where can the Achronix JESD204C IP core be used?
Applications include 5G and 6G wireless infrastructure, radar, electronic warfare, test and measurement, medical imaging and scientific instrumentation.
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