Renesas has launched the TP65H020G4PLSGBD, a 650 V GaN FET that uses an 8 × 8 mm dual-side-cooled PQFN package for high-density power conversion.
Based on the company’s Gen IV Plus GaN technology, the new D-mode device has an on-resistance of 20 mΩ and is aimed at 800 V power architectures used in high-density data center systems. Target applications include the intermediate bus converter stage that steps an 800 V rail down to 48 V, 12 V or 6 V, as well as battery backup and capacitor bank stages.
The packaging is a central part of the design. Rather than removing heat only through the top of the device, the new PQFN supports cooling from both sides while occupying considerably less board area than Renesas’ existing TOLT package.
Dual-Side Cooling in an 8 × 8 mm Footprint
The TP65H020G4PLSGBD package is 57% smaller than the existing 10 × 15 mm TOLT package. Renesas also specifies a 10% reduction in top-side thermal impedance.
That combination is intended for power stages where available PCB area and thermal performance are both becoming constraints. The smaller 8 × 8 mm footprint leaves more room for power devices and surrounding circuitry, while dual-side cooling gives designers another path for removing heat from the GaN FET.
Renesas developed the PQFN footprint in collaboration with AI infrastructure customers and is positioning the device for high-density 800 V DC/DC conversion.
The GaN FET itself combines the 20 mΩ on-resistance with low gate charge and output capacitance. It also includes a freewheeling diode with minimal reverse recovery and has a high threshold voltage that allows operation without a negative gate bias.
According to Renesas, the device can be driven using a standard silicon gate driver and can operate into the MHz switching range.
6 kW Reference Design Reaches 2.6 kW/in³
Renesas has already used the new package in a 6 kW, 800 V-to-48 V LLC DC transformer reference design controlled by an RA6T3 MCU.
The company reports a power density of 2.6 kW/in³ and measured full-load efficiency 0.21% higher than an equivalent board using its TOLT-packaged GaN device. Renesas also says the smaller package reduces PCB area and allows a better-matched layout across the FETs. The same 8 × 8 mm platform is being used in 800 V-to-12 V and 800 V-to-6 V intermediate bus converter reference designs.
The TP65H020G4PLSGBD is sampling now, with mass production planned for mid-2027.
Learn more and read the original announcement at renesas.com.
Technology Overview
The Renesas TP65H020G4PLSGBD is a 650 V, 20 mΩ D-mode GaN FET in an 8 × 8 mm dual-side-cooled PQFN package. Based on Gen IV Plus GaN technology, it targets high-density 800 V power conversion and can be driven using a standard silicon gate driver.
FAQs
What is different about the TP65H020G4PLSGBD package?
It uses an 8 × 8 mm dual-side-cooled PQFN package that dissipates heat through both the top and bottom. Renesas says the footprint is 57% smaller than its existing 10 × 15 mm TOLT package.
What applications is the new 650 V GaN FET designed for?
Renesas is targeting 800 V data center power architectures, including intermediate bus converters that step down to 48 V, 12 V or 6 V, as well as battery backup and capacitor bank stages.
What performance has Renesas demonstrated with the device?
A 6 kW, 800 V-to-48 V LLC DC transformer reference design reached 2.6 kW/in³ power density. Renesas measured full-load efficiency 0.21% higher than an equivalent TOLT-based board.
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