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SemiQ Introduces Gen4 SiC MOSFETs with 9 mΩ On-Resistance

The new 750 V and 1200 V devices feature a redesigned cell structure, reducing on-resistance and switching energy for high-power conversion applications.

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SemiQ has introduced its fourth-generation QSiC silicon carbide MOSFETs, expanding its power semiconductor range with new 750 V and 1200 V devices available in discrete packages and bare-die form. The Gen4 family targets EV charging infrastructure, solar inverters, industrial drives and high-voltage power converters.

The new generation incorporates an optimized cell topology with a 36% reduction in cell pitch, alongside changes to the JFET and P-well implantation. According to SemiQ, these improvements reduce specific on-resistance by 23% compared with previous generations, increasing current capability while reducing conduction losses.

The 1200 V devices achieve an on-resistance of 11 mΩ, a 21% reduction compared with SemiQ's Gen3 technology. The company also reports a reduction of more than 11% in total switching energy, while retaining the same 5 × 5 mm die dimensions as its previous-generation 1200 V MOSFETs.

Reduced Cell Pitch and On-Resistance

The reduction in cell pitch is one of the main changes introduced with Gen4 technology. Combined with the optimized JFET and P-well implantation, it has allowed SemiQ to improve conduction performance without increasing the die size of its 1200 V devices.

The lower on-resistance reduces conduction losses in high-current power conversion circuits, while the reported improvement in switching energy addresses losses during device turn-on and turn-off. Both are relevant to applications such as EV chargers, solar inverters and industrial motor drives, where electrical losses contribute to thermal management requirements.

Alongside the improved 1200 V MOSFETs, SemiQ has introduced a 750 V device for the first time in its QSiC Gen4 lineup. The new voltage class offers an on-resistance of 9 mΩ and a reported total switching energy of 871 µJ.

Gate-Oxide Screening and Package Options

SemiQ subjects its Gen4 MOSFET dies to wafer-level gate-oxide burn-in screening, using voltages exceeding 1400 V for the 1200 V devices and 800 V for the 750 V versions. Both voltage classes also undergo avalanche testing to 800 mJ.

The family consists of four part numbers. The GP4T009A075H and GP4T011A120H are the packaged 750 V and 1200 V versions, while the GP4T009A075X and GP4T011A120X are supplied as bare dies.

Both packaged devices use a four-pin TO-247-4L package, with the bare-die options available for applications requiring a different assembly approach.

SemiQ is targeting the new MOSFETs at EV charging, high-voltage DC/DC and DC/AC converters, solar inverters, switch-mode power supplies, uninterruptible power supplies, induction heating, welding and motor drives.

The Gen4 SiC MOSFETs are available now.

Learn more and read the original announcement at semiq.com.


Technology Overview

SemiQ's fourth-generation QSiC MOSFETs are 750 V and 1200 V silicon carbide power devices featuring a 36% reduction in cell pitch and optimized JFET and P-well implantation. The 1200 V devices offer 11 mΩ on-resistance, 21% lower than the previous generation, while the new 750 V devices achieve 9 mΩ. Both voltage classes undergo wafer-level gate-oxide burn-in and 800 mJ avalanche testing. The MOSFETs are available in TO-247-4L packages and bare-die versions.

FAQs

What improvements does SemiQ's Gen4 SiC technology offer over Gen3?

SemiQ has reduced cell pitch by 36% and optimized the JFET and P-well implantation. The changes reduce specific on-resistance by 23%, while the 1200 V devices achieve a 21% reduction in on-resistance and a reported improvement of more than 11% in total switching energy.

What are the differences between SemiQ's 750 V and 1200 V Gen4 MOSFETs?

The 750 V devices have an on-resistance of 9 mΩ, while the 1200 V versions offer 11 mΩ. Both voltage classes are available in four-pin TO-247-4L packages or as bare dies.

What reliability testing do the Gen4 SiC MOSFETs undergo?

The MOSFET dies undergo wafer-level gate-oxide burn-in screening at voltages exceeding 1400 V for the 1200 V devices and 800 V for the 750 V devices. Both are also avalanche tested to 800 mJ.

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