Why GAA Is Leading Future Technologies

Transistor design has been in constant evolution since the invention of the planar transistor in the mid-20th century. Planar devices were relatively simple to fabricate, well-suited to photolithography techniques of the time, and supported the rapid scaling that defined the early decades of Moore’s Law. Their two-dimensional layout made large-scale manufacturing straightforward, with consistent yields and predictable performance.

However, as transistor geometries pushed below 100 nanometres, the limitations of planar designs became increasingly apparent. At such scales, controlling the flow of electrons through the channel becomes more difficult. Leakage current increases due to short-channel effects, and the gate loses its ability to fully control the channel, reducing switching performance and increasing power consumption. As feature sizes dropped below 20nm, these issues reached critical levels.

This challenge led to the introduction of FinFETs, which raised the channel vertically and wrapped the gate around three sides. FinFETs extended the life of silicon CMOS technology, offering better electrostatic control than planar devices. But even FinFETs struggle as nodes shrink toward 3nm and below.

Gate-All-Around (GAA) FETs are the next step in this progression. In GAA architecture, the gate material completely surrounds the channel, often implemented as a stack of nanosheets or nanowires. This full gate enclosure provides significantly improved electrostatic control over the channel, minimizing leakage and improving switching behaviour. It allows designers to reduce the channel width without sacrificing performance, enabling higher transistor densities.

One of the core advantages of GAA is scalability. As devices continue to shrink, maintaining control over the channel is essential. GAA transistors offer superior gate-channel coupling compared to FinFETs, especially at sub-3nm nodes. This tighter control enables lower threshold voltages and improved sub-threshold slopes, both of which contribute to reduced power consumption.

In addition to power efficiency, GAA also delivers faster switching speeds. The enhanced gate control reduces parasitic capacitance and enables more aggressive drive current, improving performance in high-frequency applications. This makes GAA ideal for modern SoCs, AI accelerators, and mobile processors where power and performance must be carefully balanced.

Another key benefit is design flexibility. With nanosheet-based GAA, chipmakers can vary the width of the nanosheets to tune drive current for different performance and power targets. This architectural tunability is critical for heterogeneous integration and chiplet designs, where different parts of the chip may require different electrical characteristics.

Major semiconductor manufacturers, including TSMC, Samsung, and Intel, are actively transitioning to GAA at the 3nm and 2nm nodes. Samsung's Multi-Bridge-Channel FET (MBCFET) and Intel's RibbonFET are examples of commercial GAA implementations, signalling industry-wide confidence in the architecture.

Rapidus Begins Prototyping 2nm GAA Transistors

Rapidus has reached a key milestone in next-generation semiconductor manufacturing, officially beginning prototyping for its 2nm gate-all-around (GAA) transistor technology, and initial wafers are now undergoing electrical characterization at the company’s IIM-1 facility.

Located in Chitose, Japan, the Innovative Integration for Manufacturing (IIM-1) foundry is Rapidus' flagship facility, a rethinking of traditional fab operations. It’s designed for adaptive, real-time process optimization using AI and data-driven feedback loops. Central to this approach is fully single-wafer front-end processing, where each wafer is processed, measured, and used to inform adjustments to subsequent runs. This technique yields high volumes of granular data for AI model training, ultimately improving yield and reducing cycle time.

Rapidus is among the first to pursue commercial single-wafer processing, which forms the backbone of its Rapid and Unified Manufacturing Service (RUMs).

The prototyping effort also leverages Extreme Ultraviolet (EUV) lithography, essential for fabricating 2nm GAA structures. Rapidus was the first to install cutting-edge EUV tools in Japan, completing its first successful EUV exposures in April 2025, just three months after tool installation.

Since breaking ground in September 2023, Rapidus has rapidly built out IIM-1. The cleanroom was completed in 2024, and by June 2025, over 200 advanced tools were operational. The company plans to release a Process Development Kit (PDK) for its 2nm platform by Q1 2026, giving early-access customers a head start on prototyping. Mass production for the new transistors is slated for 2027.

What Technologies Could Be Next?

GAA technology represents a critical breakthrough for continuing transistor scaling, but it is far from the only path forward. As the industry pushes beyond the 2nm node, several complementary and alternative approaches are under active development, and each targets different bottlenecks in semiconductor performance, density, and energy efficiency.

One of the most promising directions is 3D chip stacking. Rather than continually shrinking features in a single plane, 3D integration allows chips to be vertically layered, increasing performance and functional density without expanding footprint. Through-Silicon Vias (TSVs) and advanced interposers enable high-speed communication between stacked dies, supporting complex system-on-package (SoP) designs. This is especially advantageous for applications such as AI, HPC, and edge computing, where memory bandwidth and compute density are critical.

3D architectures also reduce the reliance on extreme lithographic scaling. As planar transistor scaling becomes more expensive and difficult, 3D integration offers a practical way to extend Moore’s Law without shrinking gate lengths. It supports heterogeneous integration as well, allowing logic, memory, and analog components to be optimized independently and stacked as needed.

Beyond integration strategies, new vertical transistor structures are also under exploration. These devices rotate the traditional transistor layout by building the channel vertically into the silicon substrate. This allows for even greater density and may offer improved electrostatic control compared to lateral GAA designs. Samsung and other foundries have disclosed research into vertical nanosheet and nanowire structures as post-GAA candidates.

Material innovation is another frontier. Traditional silicon faces fundamental limits, especially below 2nm. Researchers are investigating 2D monolayer materials, such as molybdenum disulfide (MoS₂), tungsten diselenide (WSe₂), and other transition metal dichalcogenides (TMDs). These materials can form atomically thin channels with excellent carrier mobility and strong gate control, ideal for ultra-scaled transistors. Early prototypes have demonstrated promising results, though challenges remain in large-area synthesis, contact resistance, and integration with existing CMOS processes.

Carbon nanotubes and graphene also continue to draw interest, particularly for interconnects and niche transistor designs. While not yet mature enough for mass production, they represent a long-term opportunity for redefining semiconductor materials beyond the silicon paradigm.

In the meantime, 2nm GAA transistors remain the most practical near-term solution. They offer a solid balance of manufacturability, performance, and power efficiency, qualities essential for mobile, AI, and cloud workloads. Major fabs are investing heavily in GAA-based nodes as the foundation for the next generation of consumer and industrial electronics.

The future of semiconductors will likely be hybrid. GAA will coexist with 3D packaging, new materials, and novel architectures. The next decade may see less emphasis on shrinking transistors and more on intelligent system-level design, enabled by innovations across the stack.

The 2nm era is just beginning, and while GAA leads the charge, it's only part of a broader, more diverse roadmap shaping the future of computing.