Chinese Researchers Create New 3D DRAM Technology

The Challenge with DRAM

Dynamic Random Access Memory, or DRAM, is arguably one of the most important memory technologies to date thanks to its ability to provide computers with a fast random access area for memory. While DRAM does store program data and instructions that the CPU executes, processors first fetch those instructions into caches and registers. But as new technologies become available, demands on computing continue to grow, and this means that more memory will be required.

Traditional DRAM devices are two-dimensional planar devices which limits how many can be integrated into a single memory chip. Furthermore, DRAM relies on capacitance to store information meaning that smaller cell capacitance reduces charge retention, increasing refresh rates and making scaling more difficult. This means that modern DRAM technologies are already struggling to meet the demands of modern computing, and this will only get worse as time progresses.

One potential solution is to move towards 3D DRAM. Although some forms of 3D-stacked DRAM (for example HBM and earlier stacked designs like Hybrid Memory Cube) are already commercially available, the specific research approaches to denser vertical DRAM structures remain at prototype and research stages. However, if a widely scalable 3D DRAM technology was developed, it would have major ramifications on memory sizes in a similar fashion to 3D NAND flash memory, which saw density increases by vertically stacking cells, increasing capacity without proportionally increasing die footprint.

Chinese Researchers Create New 3D DRAM Technology

Recently, the Institute of Microelectronics of CAS announced the development of a new 3D DRAM structure that could help accelerate the creation of high-density memory devices.

In collaboration with Semiconductor Advanced Manufacturing Technologies (SAMT) Co., Ltd., and the School of Microelectronics at Shandong University, IME CAS has created a dual-gate 4F2 2T0C memory cell that not only provides a compact footprint, but also supports multiple programming schemes, including vertical and lateral writing. The new memory cell utilises an in-situ metal self-oxidation process to integrate transistors self-aligned into the memory cell, and the resulting device was able to support 4-level (2-bit) multi-level storage.

Furthermore, the team tested the new memory cell and found that the device exhibited good performance and stability, with write times of 50ns, data retention of about 300 seconds under test conditions, and stable operation up to 85°C.

Could this technology be the way forward for DRAM?

If there is one technology that I am genuinely excited for, it's what the researchers have presented here. DRAM has been struggling to increase in size for the past decade, and when looking at other memory technologies from 10 years ago, they are not much different in size today.

For example, many personal computers from 10 years ago commonly shipped with 4GB of memory, but 32GB configurations were already possible on many systems, often using the same number of memory slots (e.g., 4 × 8GB on 4‑DIMM motherboards).

But if the 3D DRAM technology demonstrated by the researchers can be made to work at scale, then this will change dramatically. Computing devices will suddenly see massive increases in RAM sizes, and this will allow for more complex applications to run.

This increase in RAM size will also enable the possibility of creating battery-backed storage devices that utilise RAM instead of flash or disks. Such a device would provide insanely fast disk operations, and would make disk IO less of a bottleneck.

Of course, only time will tell if this technology can be scaled up, but it is exciting to see what researchers are doing with DRAM.