Deca and SST Partner to Advance NVM Chiplet Architectures

Chiplets are becoming a practical way to sidestep the cost and complexity of ever-larger monolithic chips. Memory plays a big role in this shift, and Deca Technologies has teamed up with Silicon Storage Technology (SST), a Microchip subsidiary, to make non-volatile memory (NVM) chiplets easier to integrate into multi-die systems.

The collaboration combines Deca’s M-Series™ fan-out packaging and Adaptive Patterning® technology with SST’s SuperFlash® embedded flash memory. The result is a ready-to-use chiplet package that includes interface logic, design rules, and all the physical elements needed for system-level integration. Instead of designing memory blocks from scratch, customers can now drop in a self-contained NVM chiplet and focus on the rest of their architecture.

Why This Matters

Chiplet adoption is growing quickly because it allows engineers to mix process nodes, reuse proven IP, and bring products to market faster. NVM is one of the trickier parts to get right in a chiplet environment. By addressing this, Deca and SST are making heterogeneous integration more accessible.

“Chiplet integration is reshaping how the industry thinks about performance, scalability, and time to market,” said Robin Davis, VP of Strategic Engagements & Applications at Deca. “Our partnership with SST empowers customers to develop a chiplet solution that combines different chips, process nodes, sizes and even die from multiple foundries, delivering more efficient and cost-effective products.”

Technical Details

Deca’s Adaptive Patterning is central to the approach. It dynamically adjusts redistribution layer (RDL) layouts during assembly to correct for die shift and improve yield. The chiplet package also comes with simulation flows, test strategies, and manufacturing routes through Deca’s qualified partners, helping teams without advanced packaging experience move quickly from design to prototype.

SST’s SuperFlash memory is known for its low power operation and fast erase/program cycles. Wrapping it into a chiplet form factor makes it easier to place directly next to compute or controller die, improving performance and lowering latency.

Industry Impact

Both companies plan to support customers throughout the design and qualification process, reducing integration friction and helping accelerate chiplet adoption.

“As our customers push the boundaries of Moore’s Law, they are expressing greater interest in chiplet-based solutions,” said Mark Reiten, Vice President of Microchip’s licensing business unit. “This partnership aims to deliver a comprehensive package of IP, simulation tools and advanced assembly and engineering services necessary for successful chiplet development and productization.”

With this memory-centric building block, Deca and SST are filling an important gap in the chiplet ecosystem and giving designers another tool to push system performance forward.

Learn more and read the original article on www.microchip.com