Microchip’s 3 nm PCIe Gen 6 Switch Targets AI Data Flow Bottlenecks

AI servers are pushing today’s interconnects harder than ever. Every generation of GPUs and accelerators demands faster links to CPUs and memory, but latency and bandwidth still define system performance. Microchip is tackling that with the Switchtec™ Gen 6 PCIe® Fanout Switch, a new family built on a 3 nm process that brings more lanes, lower power use, and improved security to high-performance computing and AI infrastructure.

More Bandwidth, Less Overhead

PCIe 6.0 doubles the throughput of PCIe 5.0 to 64 GT/s per lane, but using that bandwidth efficiently requires more than raw speed. The Switchtec Gen 6 family supports up to 160 lanes, letting servers tie together more GPUs, CPUs, and accelerators through shorter, faster paths. That connectivity helps eliminate the underutilisation seen in older systems where compute power outran data delivery.

Inside data centres, this kind of switch functions as the central link between multiple compute devices. Instead of routing data through slower host bridges, it creates direct peer-to-peer communication between accelerators, an essential feature for AI training clusters where every microsecond counts.

New Architecture and Error Control

The move to PCIe 6.0 introduces several protocol-level upgrades. Among them, Flow Control Unit (FLIT) mode and Forward Error Correction (FEC) improve signal reliability, while dynamic resource allocation helps balance bandwidth across multiple connected devices. Together, these features make high-speed transfers more efficient, especially for small packets typical of AI workloads.

The Switchtec Gen 6 line includes 20 ports and 10 stacks, each equipped with hot- and surprise-plug controllers. It also supports Non-Transparent Bridging (NTB) for multi-host systems and multicast for distributing data to multiple endpoints in parallel.

Security and Diagnostic Capability

With more distributed compute nodes in modern AI clusters, security at the hardware layer has become critical. The new switches incorporate secure boot and a hardware root of trust based on CNSA 2.0 cryptography, offering protection against tampering and future post-quantum threats.

Engineers can monitor and fine-tune performance through Microchip’s ChipLink diagnostic suite, which connects via PCIe or sideband interfaces. The software provides detailed visibility into link behaviour, latency, and power metrics during development or deployment.

Why It Matters

For data centre designers, the biggest gains now come from improving how components talk to each other, not just how fast they compute. The Switchtec Gen 6 family represents that shift. An infrastructure-level change that improves bandwidth, lowers latency, and hardens security in one move. Built on 3 nm silicon and ready for PCIe 6.0, it positions Microchip at the core of next-generation AI and HPC connectivity.

Learn more and read the original article on www.microchip.com