NXP Launches MCX A5 MCUs with 10BASE-T1S and PQC

NXP Semiconductors has announced the MCX A5 family of microcontrollers for industrial and IoT edge applications. The new family combines an Arm Cortex-M33 core running at up to 240 MHz with an integrated 10BASE-T1S Ethernet digital PHY, topology discovery and post-quantum cryptography support.

Integrated 10BASE-T1S Ethernet is intended to extend IP-based connectivity further into industrial systems, connecting sensors, actuators and controllers over compact, low-cost multi-drop Ethernet networks. NXP says the MCX A5 is the industry's first wired MCU to implement topology discovery alongside a 10BASE-T1S digital PHY.

Topology discovery automatically identifies and maps connected devices, giving developers greater visibility across distributed industrial networks.

10BASE-T1S Connectivity for Distributed Edge Nodes

The MCX A5's integrated 10BASE-T1S digital PHY can be paired with NXP's TJF1410 Physical Medium Dependent transceiver. The TJF1410 acts as the analog front end to the MCU's digital PHY and is optimized for IEEE 802.3cg-compliant 10BASE-T1S networks.

Together, the two devices form a complete single-pair Ethernet solution for industrial automation, building automation, energy infrastructure and other distributed edge applications.

The MCX A5 family offers up to 2 MB Flash and 640 KB RAM. Connectivity interfaces include UART, I2C, I3C, SPI, CAN FD, High-Speed USB and FlexIO.

Security for Long Product Lifecycles

The family combines PSA Certified Level 3 security with support for post-quantum cryptography, including a PQC-based hardware root of trust. Security functions include secure boot, secure firmware updates, secure attestation and secure debug authentication.

NXP is targeting long-lifecycle connected products that need to address changing cybersecurity requirements over time, including requirements introduced by the European Cyber Resilience Act.

Selected MCX A5 devices also support the Rust programming language. Developers can use NXP's MCUXpresso software and tools ecosystem, including the MCUXpresso SDK with Long Term Support releases, development tools, middleware and security enablement.

The family also supports Zephyr RTOS, while NXP's FRDM development boards are available for development and evaluation. MCUXpresso support includes Visual Studio Code integration and LTS software releases.

The MCX A5 family is sampling now.

Learn more and read the original announcement at the NXP website.

Technology Overview

10BASE-T1S is a single-pair Ethernet technology designed for 10 Mbps multi-drop networks. It can be used to connect multiple distributed nodes over one twisted pair, making it relevant to industrial sensors, actuators and controllers. In the MCX A5 implementation, the MCU integrates the digital PHY while the external TJF1410 supplies the analog front end.

Post-quantum cryptography refers to cryptographic algorithms designed to remain secure against attacks using future quantum computers. The MCX A5 incorporates PQC support into its hardware root of trust alongside secure boot, firmware update, attestation and debug authentication.

FAQ

What is the NXP MCX A5?

The MCX A5 is a family of Arm Cortex-M33 microcontrollers for industrial and IoT edge applications. It integrates a 10BASE-T1S Ethernet digital PHY with topology discovery and post-quantum cryptography support.

What interfaces does the MCX A5 support?

The MCX A5 supports 10BASE-T1S Ethernet, UART, I2C, I3C, SPI, CAN FD, High-Speed USB and FlexIO. Devices are available with up to 2 MB Flash and 640 KB RAM.

How does the MCX A5 connect to a 10BASE-T1S network?

The MCU integrates the 10BASE-T1S digital PHY and can be paired with NXP's TJF1410 PMD transceiver, which supplies the analog front end for an IEEE 802.3cg-compliant 10BASE-T1S connection.