Latest News

The latest electronics news, featuring updates and announcements from leading companies in the electronic components industry. Stay informed on product releases, industry trends, and market insights.

Not A Member? Join The Club Now!

Filtering by tag: "3D integrated circuits"

Clear tag filter

Chinese University Creates 3D Chip Design Tool for Huawei’s Logic Folding Architecture

Recently we covered Huawei’s development of a LogicFolding technology to increase device density, but now researchers from China have created a tool to help convert chip designs into 3D folded structures. What exactly does the tool do and why could technologies like Logic Folding be the future for semiconductors?

3D chip design, LogicFolding architecture, Huawei semiconductors, Peking University EDA tool, electronic design automation, 3D integrated circuits, vertical chip integration, semiconductor density, Kirin processors, Tau Scaling Law, ISCAS 2026, chip layout complexity, domestic Chinese EDA tools, transistor scaling, semiconductor innovation, chip design tools, 3D chip technology

Researchers Create Multi-Function Transistor That Could Shrink Designs By 75%

In a world where reducing transistor sizes is beginning to have less of an effect on device density, researchers are trying to find new ways of packing more transistors on chips. Now, researchers claim to have created a new multi-function transistor that can shrink down designs as much as 75%.

multi-function transistor, semiconductor device, transistor shrinking, device miniaturization, negative differential transconductance, D-NDT, ZnO-Te heterojunction, frequency quadrupler, low-temperature BEOL, 3D integrated circuits, high-density electronics, AI hardware semiconductors, advanced chip integration, transistor count reduction, future semiconductor technology

Researchers Stack Active Chip Layers To Increase Transistor Count

As researchers approach the fundamental limits of transistor design, some are now looking to go up rather than down. What challenges does chip stacking face, what have researchers recently demonstrated, and why is this the future of semiconductor technologies?

chip stacking, 3D integrated circuits, monolithic 3D integration, active semiconductor layers, transistor density, vertical chip scaling, semiconductor manufacturing, CMOS stacking, nanomembrane transfer, thermal budget limitations, junctionless transistors, device density, Moore's Law, memory density, processor core count

Chinese University Creates 3D Chip Design Tool for Huawei’s Logic Folding Architecture

Researchers Create Multi-Function Transistor That Could Shrink Designs By 75%

Researchers Stack Active Chip Layers To Increase Transistor Count

Latest News

Information

Manage

Enquire