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Filtering by tag: "AI accelerators"

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Molex Impress Moves 224G Links Onto the ASIC Substrate

Molex launches Impress Co-Packaged Copper, a compression-attached substrate connector delivering 224G PAM-4 near-ASIC connectivity to reduce PCB loss and support next-generation AI and hyperscale data center architectures.

Molex, Impress Co-Packaged Copper, co-packaged optics, co-packaged copper, 224G PAM-4, near ASIC connectivity, high-speed interconnect, data center networking, AI accelerators, hyperscale architecture, substrate connector, compression connector, SerDes, 3.2T networking, signal integrity, PCB loss reduction, high-density server design

PowerLattice Develops Power Delivery Chiplet That Cuts Power by 50%

PowerLattice has emerged from stealth with a new power delivery chiplet designed for AI accelerators, GPUs, and CPUs, claiming over 50% power reduction. By integrating power delivery directly into the processor package using stacked chiplet design, on-die inductors, and software control, the approach could reshape high-performance, modular semiconductor systems.

PowerLattice, power delivery IC, power delivery chiplet, chiplet architecture, AI accelerators, GPUs, CPUs, semiconductor startups, power efficiency, advanced packaging, high-performance computing, modular semiconductors

Molex Impress Moves 224G Links Onto the ASIC Substrate

PowerLattice Develops Power Delivery Chiplet That Cuts Power by 50%

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